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MCM64PD32 ? mcm64pd64 1 motorola fast sram advance information 256k/512k pipelined burstram ? secondary cache module for pentium ? the MCM64PD32 (256k) and mcm64pd64 (512k) are designed to provide a burstable, high performance, l2 cache for the pentium microprocessor in conjunction with intel's triton ii chip set. the MCM64PD32 is configured as 32k x 64 bits and the mcm64pd64 is configured as 64k x 64 bits. both are packaged in a 160 pin card edge memory module. each module uses motorola's 3.3 v 32k x 32 burstrams and two motorola 3.3 v 32k x 8 fsram for the tag ram. bursts can be initiated with either address status processor (adsp ) or cache address status (cads ). subsequent burst addresses are generated internal to the burstram by the cache burst advance (cadv ) input pin. write cycles are internally self timed and are initiated by the rising edge of the clock (clk0) input. eight write enables are provided for byte write control. pd0 pd3 map into the triton ii chip set for autoconfiguration of the cache control. ? pentiumstyle burst counter on chip ? pipelined data out ? 160 pin card edge module ? address pipeline supported by adsp disabled with e x ? all cache data and tag i/os are ttl compatible ? three state outputs ? byte write capability ? fast module clock rate: 66 mhz ? fast sram access times:15 ns for tag ram 8 ns for data rams ? onecycle deselect data rams ? decoupling capacitors for each fast static ram ? high quality multilayer fr4 pwb with separate power and ground planes ? single 3.3 v +10%, 5% power supply ? burndy connector, part number: celp2x80sc3z48 ? intel coast 3.0 option iii compliant ? burst order select (bosel) option burstram is a trademark of motorola. pentium is a trademark of intel corp. this document contains information on a new product. motorola reserves the right to change or discontinue this product without notice. semiconductor technical data order this document by MCM64PD32/d MCM64PD32 mcm64pd64 160lead card edge case tbd, top view 80 43 42 1 6/14/96 ? motorola, inc. 1996
MCM64PD32 ? mcm64pd64 2 motorola fast sram MCM64PD32 block diagram bwe cadv adsp cads clk0 cg se1 32k x 32 adv k g sw se2 lbo adsp adsc dq0 dq31 zz v dd ccs v dd sa0 sa14 tio0 tio7 twe 15 13 a3 a17 gwe sgw cwe0 cwe3 sba sbd se3 ecs2 ecs1 dq0 dq31 se1 32k x 32 adv k g sw se2 lbo adsp adsc dq0 dq31 zz sa0 sa14 15 sgw sba sbd se3 dq32 dq63 cwe4 cwe7 a0 a12 dq0 dq7 a13 w a14 g 32k x 8 e tio8 tio9 tio10 v dd 3 8.2 k w 8.2 k w bosel 8.2 k w 4.7 k w
MCM64PD32 ? mcm64pd64 3 motorola fast sram mcm64pd64 block diagram bwe cadv adsp cads clk0 cg se1 32k x 32 adv k g sw se2 lbo adsp adsc dq0 dq31 zz v dd v dd sa0 sa14 tio0 tio7 twe 13 a3 a17 gwe sgw cwe0 cwe3 sba sbd se3 dq0 dq31 se1 32k x 32 adv k g sw se2 lbo adsp adsc dq0 dq31 zz sa0 sa14 15 sgw sba sbd se3 dq32 dq63 cwe4 cwe7 a0 a12 dq0 dq7 a13 w a14 g 32k x 8 e tio8 tio9 tio10 v dd 3 8.2 k w 4.7 k w bosel 8.2 k w a18 se1 32k x 32 adv k g sw se2 lbo adsp adsc dq0 dq31 zz sa0 sa14 15 sgw sba sbd se3 se1 32k x 32 adv k g sw se2 lbo adsp adsc dq0 dq31 zz sa0 sa14 sgw sba sbd se3 v dd 8.2 k w ccs clk1
MCM64PD32 ? mcm64pd64 4 motorola fast sram pin assignment 160lead card edge module (dimm) pin name pin name pin name pin name pin name 1 v ss 33 pd1 65 dq22 97 nc 129 dq47 2 tio0 34 pd3 66 dq20 98 nc 130 dq45 3 tio2 35 v ss 67 dq18 99 v ss 131 dq43 4 tio6 36 clk1 68 v dd 3 100 rsvd 132 v dd 5 5 tio4 37 v ss 69 dq16 101 a4 133 dq41 6 tio8 38 dq62 70 dq14 102 a6 134 dq39 7 v dd 3 39 v dd 3 71 dq12 103 a8 135 dq37 8 twe 40 dq60 72 v ss 104 a10 136 v ss 9 cads 41 dq58 73 dq10 105 v dd 5 137 dq35 10 v ss 42 dq56 74 dq8 106 a17 138 dq33 11 cwe4 43 v ss 75 dq6 107 v ss 139 dq31 12 cwe6 44 dq54 76 v dd 3 108 a9 140 v dd 5 13 cwe0 45 dq52 77 dq4 109 a14 141 dq29 14 cwe2 46 dq50 78 dq2 110 a15 142 dq27 15 v dd 3 47 dq48 79 dq0 111 rsvd 143 dq25 16 ccs 48 v ss 80 v ss 112 pd0 144 v ss 17 gwe 49 dq46 81 v ss 113 pd2 145 dq23 18 bwe 50 dq44 82 tio1 114 bosel 146 dq21 19 v ss 51 dq42 83 tio7 115 v ss 147 dq19 20 a3 52 v dd 3 84 tio5 116 clk0 148 v dd 5 21 a7 53 dq40 85 tio3 117 v ss 149 dq17 22 a5 54 dq38 86 tio9 118 dq63 150 dq15 23 a11 55 dq36 87 v dd 5 119 v dd 5 151 dq13 24 a16 56 v ss 88 tio10 120 dq61 152 v ss 25 v dd 3 57 dq34 89 cadv 121 dq59 153 dq11 26 a18 58 dq32 90 v ss 122 dq57 154 dq9 27 v ss 59 dq30 91 cg 123 v ss 155 dq7 28 a12 60 v dd 3 92 cwe5 124 dq55 156 v dd 5 29 a13 61 dq28 93 cwe7 125 dq53 157 dq5 30 adsp 62 dq26 94 cwe1 126 dq51 158 dq3 31 ecs1 63 dq24 95 v dd 5 127 dq49 159 dq1 32 ecs2 64 v ss 96 cwe3 128 v ss 160 v ss top view case tbd 1 42 43 80 81 122 123 160 presence detect table cache size and functionality pd0 pd1 pd2 pd3 256k pipe burst nc nc v ss nc 512k pipe burst v ss v ss nc v ss
MCM64PD32 ? mcm64pd64 5 motorola fast sram pin descriptions 160lead card edge pin locations symbol type description 20, 21, 22, 23, 24, 26, 28, 29, 101, 102, 103, 104, 106, 108, 109, 110 a3 a18 input address inputs: these inputs are registered into data rams and must meet setup and hold times. the tag ram addresses are not registered. 30 adsp input address status processor: initiates read, write, or chip deselect cycle (exceptionchip deselect dgs not occur when adsp is asserted and ccs is high. 114 bosel input burst order select: nc for interleaved burst counter. tie to ground for linear burst counter. 18 bwe input byte write enable: to be used in future modules. 9 cads input cache address status: initiates read, write, or chip deselect cycle. 89 cadv input cache burst advance: increments address count in accordance with interleaved count style. 16 ccs input chip select: active low chip enable for data rams. 91 cg input cache output enable: active low asynchronous input. low enables output buffers (dq pins) high dqx pins are high impedance. 36, 116 clk0, clk1 input clock: this signal registers the address, data in, and all control signals except cg . 11, 12, 13, 14, 92, 93, 94, 96 cwe0 cwe7 input cache data byte write enable: active low write signal for data rams. 38, 40, 41, 42, 44, 45, 46, 47, 49, 50, 51, 53, 54, 55, 57, 58, 59, 61, 62, 63, 65, 66, 67, 69, 70, 71, 73, 74, 75, 77, 78, 79, 118, 120, 121, 122, 124, 125, 126, 127, 129, 130, 131, 133, 134, 135, 137, 138, 139, 141, 142, 143, 145, 146, 147, 149, 150, 151, 153, 154, 155, 157, 158, 159 dq0 dq63 i/o synchronous data i/o: drives data out of data rams during read cycles. stores data to data rams during write cycles. 31, 32 ecs1 , ecs2 input expansion chip select 17 gwe input global write enable: to be used in future modules. 33, 34, 112, 113 pd0 pd3 e presence detect: see presence detect table 2, 3, 4, 5, 6, 82, 83, 84, 85, 86, 88 tio0 tio10 i/o tag ram i/o: drives data out during tag compare cycles. stores data to tag ram during tag write cycles. 8 twe input tag write enable: active low write signal for tag rams. 7, 15, 25, 39, 52, 60, 68, 76 v dd 3 supply power supply: 3.3 v + 10%, 5%. 87, 95, 105, 119, 132, 140, 148, 156 v dd 5 supply power supply: 5.0 v 5%. 1, 10, 19, 27, 35, 37, 43, 48, 56, 64, 72, 80, 81, 90, 99, 107, 115, 117, 123, 128, 136, 144, 152, 160 v ss supply ground. 100, 111 rsvd e no connection: reserved for future use. 97, 98 nc e no connection: there is no connection to the module.
MCM64PD32 ? mcm64pd64 6 motorola fast sram synchronous truth table (see notes 1, 2, and 3) ccs adsp cads cadv cwex clk0 address used operation h x l x x lh n/a deselected l l x x x lh external address read cycle, begin burst l h l x l lh external address write cycle, begin burst l h l x h lh external address read cycle, begin burst x h h l l lh next address write cycle, continue burst x h h l h lh next address read cycle, continue burst x h h h l lh current address write cycle, suspend burst x h h h h lh current address read cycle, suspend burst h x h l l lh next address write cycle, continue burst h x h l h lh next address read cycle, continue burst h x h h l lh current address write cycle, suspend burst h x h h h lh current address read cycle, suspend burst notes: 1. x means don't care. 2. all inputs except cg must meet setup and hold times for the lowtohigh transition of clock (clk0/1). 3. wait states are inserted by suspending burst. asynchronous truth table (see notes 1 and 2) operation cg i/o status read l data out read h highz write x highz e data in deselected x highz notes: 1. x means don't care. 2. for a write operation following a read operation, g must be high before the input data required setup time and held high through the input data hold time. dc absolute maximum ratings (voltages referenced to v ss = 0 v) rating symbol value unit power supply voltage v dd 3 0.5 to + 4.6 v voltage relative to v ss v in , v out v ss 0.5 to v dd 3 + 0.5 v output current (per i/o) i out 20 ma temperature under bias t bias 10 to + 85 c operating temperature t a 0 to +70 c storage temperature t stg 65 to + 150 c note: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended oper- ating conditions. exposure to higher than recommended voltages for extended periods of time could affect device reliability. this device contains circuitry to protect the inputs against damage due to high static volt- ages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maxi- mum rated voltages to this highimpedance circuit. this bicmos memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. this device contains circuitry that will ensure the output devices are in highz at power up.
MCM64PD32 ? mcm64pd64 7 motorola fast sram dc operating conditions and characteristics (v dd = 3.3 v + 10%, 5%, t j = 20 to + 110 c, unless otherwise noted) recommended operating conditions (voltages referenced to v ss = 0 v) parameter symbol min max unit notes supply voltage (operating voltage range) v dd 3.135 3.6 v 1 input high voltage v ih 2.0 v dd + 0.3 v 2 input low voltage v il 0.5 0.8 v 3 notes: 1. jedec specification 81a specifies 0.3 v tolerance for v dd . 2. v ih (max) = v dd + 0.3 v dc; v ih (max) = v dd + 2.0 v ac (pulse width 20 ns) for i 20.0 ma. 3. v il (min) = 0.5 v dc; v il (min) = 2.0 v ac (pulse width 20 ns) for i 20.0 ma. dc characteristics parameter symbol min max unit notes input leakage current (all inputs, v in = 0 to v dd 3) i lkg(i) e 1.0 m a output leakage current (cg = v ih ) i lkg(o) e 1.0 m a ttl output low voltage (i ol = + 8.0 ma) v ol e 0.4 v 1 ttl output high voltage (i oh = 4.0 ma) v oh 2.4 e v 1 notes: 1. champing diodes exist to v ss and v dd . power supply currents parameter symbol max unit ac supply current (cg = v ih , ccs = v il , i out = 0 ma, all inputs = v il or v ih , MCM64PD32 v il = 0.0 v and v ih 3.0 v, cycle time t khkh min) mcm64pd64 i dda 720 880 ma ac standby current (cg = v ih , ccs = v il , i out = 0 ma, all inputs = v il or v ih , MCM64PD32 v il = 0.0 v and v ih 3.0 v, cycle time t khkh min) mcm64pd64 i sb1 200 490 ma capacitance (f = 1.0 mhz, dv = 3.0 v, t j = 20 to 110 c, periodically sampled rather than 100% tested) parameter symbol max unit input capacitance MCM64PD32 mcm64pd64 c in 22 32 pf input/output capacitance (dq0 dq63) MCM64PD32 mcm64pd64 c i/o 8 16 pf
MCM64PD32 ? mcm64pd64 8 motorola fast sram data rams ac operating conditions and characteristics (v dd = 3.3 v + 10%, 5% t j = 20 to + 110 c, unless otherwise noted) input timing measurement reference level 1.5 v . . . . . . . . . . . . . . . input pulse levels 0 to 3.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input rise/fall time 2 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output timing reference level 1.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . output load see figure 3 unless otherwise noted . . . . . . . . . . . . . . 2.4 input waveform t r test point (unloaded output) output buffer 2.4 0.4 0.4 output waveform output load t f unloaded rise and fall time measurement notes: 1. input waveform has a slew rate of 1 v/ns. 2. rise time is measured from 0.4 v to 2.4 v unloaded. 3. fall time is measured from 2.4 v to 0.4 v unloaded. figure 1. unloaded rise and fall time characterization
MCM64PD32 ? mcm64pd64 9 motorola fast sram data rams read/write cycle timing (see notes 1, 2, and 3) MCM64PD3266 parameter symbol min max unit notes cycle time t khkh 15 e ns clock access time t khqv e 8 ns 5 output enable to output valid t glqv e 6 ns 5 clock high to output active t khqx1 0 e ns 5, 7 clock high to output change t khqx2 2 e ns 5, 7 output enable to output active t glqx 0 e ns 5, 7 output disable to q highz t ghqz e 8 ns 6, 7 clock high to q highz t khqz 2 8 ns 6, 7 clock high pulse width t khkl 5 e ns clock low pulse width t klkh 5 e ns setup times: address address status data in write address advance chip enable t avkh t adsvkh t dvkh t wvkh t advvkh t evkh 2.5 e ns 4 hold times: address address status data in write address advance chip enable t khax t khadsx t khdx t khwx t khadvx t khex 0.5 e ns 4 notes: 1. write applies to all sbx , sw , and sgw signals when the chip is selected and adsp high. 2. chip enable applies to all se1 , se2 and se3 signals whenever adsp or adsc is asserted. 3. all read and write cycle timings are referenced from k or g . 4. g is a don't care after write cycle begins. to prevent bus contention, g should be negated prior to start of write cycle. 5. tested per ac test load. 6. measured at 200 mv from steady state. tested per highz test load. 7. this parameter is sampled and is not 100% tested.
MCM64PD32 ? mcm64pd64 10 motorola fast sram test point 3.6 3.135 2.8 1.65 1.4 0 0 40 120 test point v dd 1.65 1.8 0.3 0 0 46 120 current (ma) current (ma) voltage (v) voltage (v) voltage (v) pullup i (ma) min i (ma) max 0.5 0 1.4 1.65 2 3.135 3.6 40 40 40 37 28 0 0 120 120 120 104 81 20 0 voltage (v) pulldown i (ma) min i (ma) max 0.5 0 0.5 1 1.65 1.8 3.6 4 34 0 17 35 45 46 46 46 126 0 47 90 114 120 120 120 (a) pullup (b) pulldown 5 5 80 dc drive point ac drive point ac drive point dc drive point 80 notes: 1. driver impedance @ 1.65 v = 15.9 to 44.6 w . 2. meets the temperature and voltage range specified in dc characteristics tables. 3. this drawing is not to scale. comparisons should be made to the table in figure 2a. notes: 1. driver impedance @ 1.65 v = 15.9 to 44.6 w . 2. meets the temperature and voltage range specified in dc characteristics tables. 3. this drawing is not to scale. comparisons should be made to the table in figure 2b. figure 2. output buffer characteristics
MCM64PD32 ? mcm64pd64 11 motorola fast sram burst read single read cads t khkl t khkh dqx esc1 clk0, clk1 adsp cadv q(a) burst write adsp, ax ax ab data rams read/write cycles t klkh cd ccs w q(b) q(b+1) t khqv burst wraps around q(b+2) q(b+3) q(b) d(c) d(c+1) d(c+2) d(c+3) q(d) t khqv deselected single read esc1 ignored cg t khqx1 t khqx2 t ghqz t glqx q(n1) t khqz (address) note: w low = gwe low and/or bwe and cwex low.
MCM64PD32 ? mcm64pd64 12 motorola fast sram tag ram ac operating conditions and characteristics (v dd = 3.3 v 0.3 v, t j = 20 to + 110 c, unless otherwise noted) input timing measurement reference level 1.5 v . . . . . . . . . . . . . . . input pulse levels 0 to 3.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input rise/fall time 3 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output timing measurement reference level 1.5 v . . . . . . . . . . . . . output load figure 3a unless otherwise noted . . . . . . . . . . . . . . . . . tag ram read cycle (see note 1 and 5) 15 parameter symbol min max unit notes read cycle time t avav 15 e ns 2 address access time t avqv e 15 ns output hold from address change t axqx 4 e ns 3, 4 notes: 1. cwe is high for read cycle. 2. all timings are referenced from the last valid address to the first address transition. 3. transition is measured 500 mv from steadystate voltage with load of figure 3b. 4. this parameter is sampled and not 100% tested. 5. device is continuously selected (cg = v il ). tag ram read cycle (see note 5) q (data out) ax (address) data valid previous data valid t avav t axqx t avqv output z 0 = 50 w 50 w v l = 1.5 v (a) (b) 5 pf +3.3 v output 351 w 317 w timing limits the table of timing values shows either a minimum or a maximum limit for each param- eter. input requirements are specified from the external system point of view. thus, ad- dress setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). on the other hand, responses from the memory are specified from the device point of view. thus, the access time is shown as a maximum since the device never pro- vides data later than that time. figure 3. ac test loads
MCM64PD32 ? mcm64pd64 13 motorola fast sram tag ram write cycle (see notes 1 and 2) 15 parameter symbol min max unit notes write cycle time t avav 15 e ns 3 address setup time t avwl 0 e ns address valid to end of write t avwh 12 e ns data valid to end of write t dvwh 7 e ns data hold time t whdx 0 e ns write low to output highz t wlqz 0 7 ns 5,6,7 write high to output active t whqx 4 e ns 5,6,7 write recovery time t whax 0 e ns notes: 1. a write occurs when cwe is low. 2. if cg goes low coincident with or after cwe goes low, the output will remain in a high impedance state. 3. all timings are referenced from the last valid address to the first address transition. 4. if cg v ih , the output will remain in a high impedance state. 5. at any given voltage and temperature, t wlqz (max) is less than t whqx (min), both for a given device and from device to device. 6. transition is measured 500 mv from steadystate voltage with load of figure 3b. 7. this parameter is sampled and not 100% tested. tag ram write cycle (see notes 1 and 2) data valid t dvwh t avwl t avwh t avav t whax t wlwh t whdx t wlqz t whqx high z high z ax (address) twe q (data out) d (data in)
MCM64PD32 ? mcm64pd64 14 motorola fast sram ordering information (order by full part number) 64pd32 mcm 64pd64 xx xx motorola memory prefix part number full part number e MCM64PD32sg66 mcm64pd64sg66 speed (66 = 66 mhz) package (sg = gold pad simm)
MCM64PD32 ? mcm64pd64 15 motorola fast sram package dimensions 160lead card edge module case tbd m p (n) a side view e l k r 160x h 160x r w d 160x 156x y l 0.004 (0.1) x s t dim min max min max millimeters inches a 4.330 4.350 109.98 110.49 b 1.120 1.140 28.45 28.96 c 0.454 11.53 d 0.033 0.037 0.84 0.94 e 2.265 2.275 57.53 57.79 f 0.075 bsc 1.91 bsc g 0.050 bsc 1.27 bsc h 0.030 0.51 j 0.055 0.069 1.40 1.75 k 0.210 5.33 l 1.955 1.965 49.66 49.91 m 2.155 2.165 54.74 54.99 n 0.110 ref 2.79 ref p 0.300 7.62 r 0.492 0.512 7.24 7.75 v 0.300 7.62 w 0.040 0.060 1.02 1.52 ab 0.262 6.66 ac 0.072 0.076 1.83 1.93 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. card thickness applies across tabs and includes plating and/or metallization. 4. dimensions c and v define a doublesided module. 5. dimension ab defines optional singlesided module. 6. straightness callout applies to tab area only. g 2x back view component view aa ac f x y b view aa min .285 inches, component 80 43 42 1 area front view v note 4 ab note 5 j note 6 m 0.012 (0.3) t area 160 123 122 81 c note 4 note: case outline number to be determined. max .305 inches
MCM64PD32 ? mcm64pd64 16 motorola fast sram motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, 6f seibubutsuryucenter, p.o. box 20912; phoenix, arizona 85036. 18004412447 or 6023035454 3142 tatsumi kotoku, tokyo 135, japan. 038135218315 mfax : rmfax0@email.sps.mot.com touchtone 6 022446609 asia / pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, internet : http://designnet.com 51 ting kok r oad, tai po, n.t., hong kong. 85226629298 MCM64PD32/d
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